PolyU Develops Quantum-Tunnelling Transistor to Overcome Chip Development Barriers

A PolyU-led research team has engineered a tunnelling field-effect transistor using 2D nanomaterials that breaks the Boltzmann limit, enabling ultra-low-power, high-performance integrated circuits for next-generation AI chips.

Phoenix Metrowire Staff
Technology

The Hong Kong Polytechnic University (PolyU) has announced a breakthrough in transistor technology that could redefine the future of integrated circuits and artificial intelligence (AI) chips. A research team led by Prof. Jianhua Hao, Head of the Department of Physics and Materials and Chair Professor of Materials Physics and Devices at PolyU, has engineered a novel tunnelling field-effect transistor (TFET) that overcomes the physical limitations of conventional semiconductors. The findings, published in the prestigious journal Science, represent a significant step toward energy-efficient computing and advanced semiconductor applications.

Conventional transistors operate via thermionic emission, which requires a minimum gate voltage of 60 millivolts (mV) at room temperature. This fundamental constraint, known as the Boltzmann limit, restricts the subthreshold swing (SS) to values no lower than 60 mV per decade, thereby limiting the energy efficiency of traditional transistors. As the demand for more powerful computing grows, this barrier has become a critical bottleneck.

Prof. Hao’s team adopted quantum tunnelling to bypass this limit. By creating ultra-thin heterostructures of 2D bismuth and indium selenide alternating layers using pulsed laser deposition, they transformed the normally semi-metallic bismuth into a semiconductor in its 2D form. This allowed charge carriers to tunnel efficiently into indium selenide, achieving SS values well below the 60 mV per decade limit. The device operates at room temperature on silicon substrates and requires a gate-voltage range of only 160 mV, compared to the 800 mV needed in conventional designs.

The breakthrough resolves a longstanding challenge in experimental TFETs: delivering a high output current alongside an exceptionally high ON/OFF current ratio. This combination enables the device to drive multiple downstream logic gates and reduce circuit delays, making it practical for real-world applications. The research was conducted in collaboration with the National University of Singapore, The Hong Kong University of Science and Technology, Peking University, and the Singapore University of Technology and Design.

The implications of this development are profound. As noted by Prof. Hao, “By adopting quantum tunnelling, our TFET breaks through this boundary, paving the way for ultra-low-power, high-performance integrated circuits essential for emerging AI chips and advanced semiconductor applications.” This could lead to more energy-efficient data centres, longer-lasting battery-powered devices, and more capable AI systems that consume less power.

The technology is particularly timely as the semiconductor industry faces physical limits in scaling down transistors. By offering a fundamentally different approach, this TFET could extend the roadmap for Moore’s Law, enabling continued improvements in computing power without the corresponding increase in energy consumption. The collaboration between multiple institutions underscores the global effort to advance semiconductor technology, and PolyU’s leadership in this area highlights its growing role in cutting-edge materials research.

As the industry looks toward the next generation of microelectronics, this quantum-tunnelling transistor offers a promising path forward, potentially reshaping the landscape of AI hardware and integrated circuit design.

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